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LHF08CTE
DC Characteristics (Continued)
28
V CC =2.7V
V CC =3.3V
V CC =5V
Test
Sym.
Parameter
Notes Min.
Max.
Min.
Max.
Min.
Max. Unit
Conditions
V IL
V IH
Input Low Voltage
Input High Voltage
7
7
-0.5
2.0
0.8
V CC
+0.5
-0.5
2.0
0.8
V CC
+0.5
-0.5
2.0
0.8
V CC
+0.5
V
V
V OL
V OH1
V OH2
Output Low Voltage
Output High Voltage
(TTL)
Output High Voltage
(CMOS)
3,7
3,7
3,7
2.4
0.85
V CC
0.4
2.4
0.85
V CC
0.4
2.4
0.85
V CC
0.45
V
V
V
V CC =V CC Min.
I OL =5.8mA(V CC =5V)
I OL =2.0mA
(V CC =3.3V, 2.7V)
V CC =V CC Min.
I OH =-2.5mA(V CC =5V)
I OH =-2.0mA(V CC =3.3V)
I OH =-1.5mA(V CC =2.7V)
V CC =V CC Min.
I OH =-2.0mA
V CC
-0.4
V CC
-0.4
V CC
-0.4
V
V CC =V CC Min.
I OH =-100μA
V PPLK V PP Lockout during
Normal Operations
4,7
1.5
1.5
1.5
V
V PPH1 V PP during Byte Write,
Block Erase or
?
?
3.0
3.6
?
?
V
Lock-Bit Operations
V PPH2 V PP during Byte Write,
Block Erase or
?
?
4.5
5.5
4.5
5.5
V
Lock-Bit Operations
V PPH3 V PP during Byte Write,
Block Erase or
?
?
11.4
12.6
11.4
12.6
V
Lock-Bit Operations
V LKO
V CC Lockout Voltage
2.0
2.0
2.0
V
V HH
RP# Unlock Voltage
8,9
?
?
11.4
12.6
11.4
12.6
V
Set master lock-bit
Override master and
block lock-bit
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V CC voltage and T A =+25°C.
2. I CCWS and I CCES are specified with the device de-selected. If read or byte written while in erase suspend mode,
the device’s current draw is the sum of I CCWS or I CCES and I CCR or I CCW , respectively.
3. Includes RY/BY#.
4. Block erases, byte writes, and lock-bit configurations are inhibited when V PP ≤ V PPLK , and not guaranteed in the
range between V PPLK (max.) and V PPH1 (min.), between V PPH1 (max.) and V PPH2 (min.), between V PPH2 (max.)
and V PPH3 (min.), and above V PPH3 (max.).
5. Automatic Power Savings (APS) reduces typical I CCR to 1mA at 5V V CC and 3mA at 2.7V and 3.3V V CC in static
operation.
6. CMOS inputs are either V CC ±0.2V or GND±0.2V. TTL inputs are either V IL or V IH .
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP#=V IH . Block lock-bit configuration operations are inhibited
when the master lock-bit is set and RP#=V IH . Block erases and byte writes are inhibited when the corresponding
block-lock bit is set and RP#=V IH . Block erase, byte write, and lock-bit configuration operations are not
guaranteed with V CC <3.0V or V IH <RP#<V HH and should not be attempted.
9. RP# connection to a V HH supply is allowed for a maximum cumulative period of 80 hours.
Rev. 1.3
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